| Product
Definition |
-
Architectural definitions and specifications
- Design
ground rules generation
|
-
Technology evaluation/vendor selection
|
| Design |
-
RTL code generation (Verilog and VHDL)
-
High-speed interface design
-
Multiple clock domain design
-
Logic synthesis
-
Verification
|
-
Testbench generation
-
Functional and formal verification
- Code
coverage analysis
- Bus
functional models
|
|
Pre-Layout |
- Static
timing analysis
- Signal
integrity analysis (ASIC and System)
-
High-speed clock design
|
-
Testability (DFT, scan, logic, and RAM BIST, JTAG)
- HSPICE
modeling
|
| Layout |
-
Floorplanning
- Clock
tree synthesis
|
- Physical
synthesis
-
Placement and Routing
|
| ASIC Foundry Interface |
- ASIC
foundry release processing (based on extensive
experience working with leading-edge foundries)
- Texas
Instruments certified design center
|
- IBM
Microelectronics ASOK® and ChipBench® release processing
|